The present invention relates to parallel decimal multiplication hardware and more specifically, to a system and method of parallel decimal multiplication with a 3× generator.
Decimal multiplication is important for commercial applications. However, the difference in rounding operations between binary arithmetic and decimal arithmetic makes it hard to emulate decimal arithmetic in binary multiplication computer hardware. Conventional commercial decimal multiplication algorithms perform computations with digit-at-a-time multiplication to form partial products that are summed together. This digit-at-a-time multiplication requires many machine cycles and is considerably slower than current parallel decimal multiplication algorithms used in the binary multiplication computer hardware. Yet, current parallel decimal multiplication algorithms do not solve the issues with digit-at-a-time multiplication, as the current parallel decimal multiplication algorithms require significant increases in a number of partial product terms generated (as both of the operands are expanded), which also cause delays in the binary multiplication computer hardware.